1. Field of the Invention
The present invention relates generally to a multi-bit dynamic random access memory cell and specifically to an improved multi-bit dynamic random access memory cell and method of operation so that more data per integrated circuit surface area can be stored compared to existing dynamic random access memory cells.
2. Description of the Prior Art
In the prior art, several dynamic access memory cells are provided. In one such embodiment of the prior art shown in FIG. 1, the DRAM cell has three transistors and is normally called a three-transistor (3-T) cell circuit. Charge is stored on Capacitor C.sub.1 and the amount of stored charge determines what binary unit (either a 1 or a 0) is stored in the cell. Since this DRAM cell is the first widely used dynamic memory cell, its operation is well known to those who are well knowledgeable in this art.
Another prior art embodiment of a DRAM cell is shown in FIG. 2. This specific DRAM cell uses one transistor T.sub.30 and hence it is normally called a one-transistor (1-T) DRAM cell. It is the most widely used DRAM cell in industry today. Memory cell operation is also well known to those who are knowledgeable in this art.
Both the DRAM cells of FIG. 1 and FIG. 2 have drawbacks. The 3-T DRAM cell occupies a far bigger surface area on the integrated circuit chip so that the cost of storing a single binary bit per unit surface area is very high. In addition, considerable power savings would be realized if the 3-T DRAM cell could be reduced in area. Another drawback to this 3-T DRAM cell is that it stores only a single binary bit per cell so that there is no way currently available to increase the bit density.
With regard to the 1-T DRAM cell of FIG. 2, the biggest drawback is that this is also a one bit per memory cell device so that the number of total binary bits stored in an integrated circuit chip composed of these memory cells is equal to the total number of memory cells on the IC chip. Theoretically and practically, considerably more bit number per unit IC surface area could be realized if more than one binary bit could be stored in a one-transistor memory cell of FIG. 2.
Several attempts at building a multi-bit one-transistor DRAM cell in order to increase bit density have been undertaken in recent years. One such undertaking is described by Betty Prince in her textbook titled Semiconductor Memories: a handbook of design, manufacture and application/ Second Edition, published by Wiley on pages 332 to 336. She describes a HITACHI design and operation of a multi-bit (Multi-level) single transistor DRAM cell shown in FIG. 3A. FIG. 3B shows the staircase pulse generator and FIG. 3C shows the "Read" operation timing chart of the staircase pulse generator, all as chosen by Prince with permission of the Institute of Electrical and Electronics Engineers. As shown in the "Read" operation timing chart of FIG. 3C, when the column strobe (CS) becomes low, the staircase pulse starts to ascend and it is applied to the selected word line. The dummy word line meanwhile is driven by a half-step staircase pulse so that a half-reference voltage is read out from the dummy cell. The sense amplifier detects the signal and sends it to the column register, where the data are stored in the form of a 4-bit binary code. A data-transfer request signal (DTR) is generated when the four bits in each memory cell have been transferred to the data input and output terminals through the error correction circuit.
The bandgap reference voltage regulator protects the DRAM cell against power supply irregularities and temperature fluctuations so that the small signal voltage is accurately maintained. A refresh oscillator and an address counter are implemented on chip to perform self-refresh operation. If a read-write request comes during a refresh cycle, the request is delayed until the end of the refresh cycle.
This particular multi-bit or multi-level DRAM cell design by HITACHI had the one major drawback of the potential for soft error due to the small amount of charge that was stored in each of the four levels in the individual cell and also due to the fact that each incident alpha particle destroyed four bits of data in a cell and all other cells. Another drawback was the slow speed of operation. Random block operation is in the range of 100 microseconds and serial data rate is in the range of 210 nanoseconds. Other factors such as the slow rate of conversion between multi-level data and binary data inherently slow due to the slow iterative operation of the sense circuit.
Yet another attempt at building a multi-bit (multi-level) single transistor DRAM cell for the purpose of increasing stored bit density per unit surface area was made by TOSHIBA and is described by the above-named author in the paper quoted above. The design was based on a 2 bit per-cell DRAM in which four levels were stored in every cell. The chip, intended for the embedded memory in logic application market used a 512K cell design to give a 1-Megabit DRAM capacity. At a chip size of 37.8 square millimeters compared to the typical 1-Megabit DRAM Chip Size of about 55 square millimeters it was originally intended to improve the bit density over typical 1-Megabit DRAM. However if this memory cell is used to make a standard 1-Megabit DRAM with about 55 percent array efficiency, the chip size is about 32 square millimeters. The real comparison in density then is between 32 square millimeters for a standard 1-Megabit DRAM with this cell size and 37.8 square millimeters for the Multi-bit (multi-level) 1-Megabit DRAM.
Thus there is no chip size advantage of the multi-bit DRAM cell over existing standard DRAM cells in terms of bit density.
Several other attempts at multi-bit memory storage using other than capacitor based storage memory cells have been attempted. In U. S. patent application Ser. No. 08/414,383 filed Mar. 31, 1995 in the names of the present applicant and currently assigned to Hyundai Electronics Industries Co. Ltd., there is described a ferromagnetic memory cell apparatus and method for multi-bit storage for use as DRAM, SRAM or EEPROM cells on an integrated circuit chip, as further indication of the need to increase storage bit density in digital integrated circuit memory systems.